Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

• Autores: A.N. Tallarico, S. Reggiani, P. Magnone, Giorgio Croci, R. Depetro, P. Gattari, E. Sangiorgi, C. Fiegna
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 76-77, 2017, págs. 475-479
• Idioma: inglés
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• Resumen

  • Abstract In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.