Method for evaluation of transient-fault detection techniques

• Autores: R.A. Camponogara Viera, R. Possamai Bastos, J.-M. Dutertre, P. Maurine, R. Iga Jadue
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 76-77, 2017, págs. 68-74
• Idioma: inglés
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• Resumen

  • Abstract This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Furthermore, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements.