Design of a pipelined multiplier chip as the kernel of a vector processing architecture

• Autores: Dante Augusto Couto Barone
• Localización: Panel '92: actas, XVIII Conferencia Latinoamericana de Informática, 1992, págs. 319-327
• Idioma: español
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• Resumen

  • This paper describes the design of a pipelined multiplier chip, named TREVO. This chip constitutes a major element in a vector processing architecture, which is being researched in the Instituto de Informática of the Federal University of Rio Grande do Sul- Brazil, en the context of the Cp2 project.