Impact of planarized gate electrode in bottom-gate thin-film transistors

• M.A. Domínguez ^[1] ; P. Rosales ^[2] ; A. Torres ^[2] ; F. Flores ^[1] ; J.A. Luna ^[1] ; S. Alcántara ^[1] ; M. Moreno ^[2]
  1. [1] Benemérita Universidad Autónoma de Puebla

     Benemérita Universidad Autónoma de Puebla

     México

     
  2. [2] National Institute for Astrophysics, Optics and Electronics, Puebla, México
• Localización: Revista Mexicana de Física, ISSN-e 0035-001X, Vol. 62, Nº. 3, 2016, págs. 223-228
• Idioma: inglés
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• Resumen

  • In this work, the fabrication of bottom-gate TFTs with unplanarized and planarized gate electrode are reported, as well simulations of the impact of the gate planarization in the TFTs are presented. Previously in literature, a reduction of the contact resistance has been attributed to this planarized structure. In order to provide a physical explanation of this improvement, the electrical performance of ambipolar a-SiGe:H TFTs with planarized gate electrode by Spin-On Glass is compared with unplanarized ambipolar a-SiGe:H TFTs. Then, the properties in the main device interfaces are analyzed by physically-based simulations. The planarized TFTs have better characteristics such as field-effect mobility, on-current, threshold voltage and on/off-current ratio which are consequence of the improved contact resistance.