Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
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Yu-Chiun Lin [1] ; Shi-Yu Huang [1]
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[1] National Tsing Hua University
National Tsing Hua University
Taiwán
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- Localización: Journal of electronic testing: Theory and applications, ISSN 0923-8174, Nº. 2, 2006, págs. 151-159
- Idioma: inglés
- Texto completo no disponible (Saber más ...)
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Resumen
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.
