IEICE transactions on information and systems

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  Año 2001, Vol. 84, Número 11

  • Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes

    N. Tsuda

    págs. 1452-1461

    

  • A Graph- Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault- Tolerant Mesh- Connected Processor Arrays

    Itsuo Takanami

    págs. 1462-1470

    

  • VLSI Yield Optimization Based on the Redundancy at the Sub- Processing- Element Level

    T. Zyhao

    págs. 1471-1475

    

  • Statistical Skew Modeling and Clock Period Optimization of Water Scale H-Tree Clock Distribution Network

    Xiaohong Jiang

    págs. 1476-1485

    

  • On the Diagnosis of Two-Dimensional Grid of Processors

    Jianjun Zhao

    págs. 1486-1499

    

  • Design of Fault Tolerant Multistage Interconnection Networks with Dilated Links

    N. Kamiura

    págs. 1500-1507

    

  • The Evolutionary Algorithm-Based Reasoning System

    M. Yasunga

    págs. 1508-1520

    

  • Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface

    B. K. Tan

    págs. 1521-1527

    

  • The Kernel-Based Pattern Recongnition System Designed by Genetic Algorithms

    M. Yasunaga

    págs. 1528-1539

    

  • Minkowski Sums of Axis-Parallel Surfaces of Revolution Defined by Slope-Monotone Curves

    M. S. Kim

    págs. 1540-1547

    

  • Multi-Party Quantum Communication Complexity with Prior Entanglements

    T. Mihara

    págs. 1548-1555

    

  • PQPCkpt: An Efficient Three Level Synchronous Chekpointing Scheme in Mobile Computing Systems

    Chih Ming Lin

    págs. 1556-1567

    

  • Sound Retrieval with Intuitive Verbal Descriptions

    S. H. Wake

    págs. 1568-1576

    

  • A Grammatical Structure of the FSN for the Recognition of Korean Price Sentences

    J. P. Ham

    págs. 1577-1579