Computational paradigm for nanoelectronics: self-assembled quantum dot cellular neural networks
S. Bandyopadhyay, K. Karahaliloglu
págs. 85-92
págs. 93-102
Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin
I. V. Thompson, P. V. Brennan
págs. 103-108
págs. 109-117
Low-power single- and double-edge-triggered flip-flops for high-speed applications
A. Afzali Kusha, A. Khademzadeh, S. H. Rasouli
págs. 118-122
págs. 123-126
págs. 127-132
págs. 133-145
págs. 146-150
Design of an area-efficient CMOS multiple-valued current comparator circuit
K. S. Yeo, C. H. Chang, Z. H. Kong
págs. 151-158
Y. Susuki, T. Hikihara
págs. 159-164
Measurement-based models of a 40 Gbit/s modulator and its electrical driver for transmitter design
S. Hoffmann
págs. 165-170
págs. 171-177
V. Parihar, M. J. Kumar
págs. 178-182
págs. 183-188
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