Parallelization and Optimization of Iterative Solvers on High Performance Architectures
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http://hdl.handle.net/10347/27230
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Título: | Parallelization and Optimization of Iterative Solvers on High Performance Architectures |
Autor/a: | Coronado Barrientos, Edoardo Emilio |
Dirección/Titoría: | García Loureiro, Antonio Jesús |
Centro/Departamento: | Universidade de Santiago de Compostela. Escola de Doutoramento Internacional (EDIUS) Universidade de Santiago de Compostela. Programa de Doutoramento en Investigación en Tecnoloxías da Información |
Palabras chave: | SpMV | Iterative solvers | |
Data: | 2021 |
Resumo: | The main objective of this thesis is to develop an optimal sparse matrix storage format and implement efficient computing kernels that accelerate the execution of the sparse matrix vector (SpMV) product on modern computer architectures. The SpMV product is an essential building brick for a myriad of numerical application codes, especially for iterative solvers and numerical simulators. Improving the performance of the SpMV product is of special interest for researchers, because it is the major bottleneck for codes where it is required. Optimizing this product on modern computer architectures requires knowledge of parallel programing paradigms, efficient parallel algorithms and a basic idea of the device architecture being targeted. |
URI: | http://hdl.handle.net/10347/27230 |
Dereitos: | Attribution-NonCommercial-NoDerivatives 4.0 Internacional |
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