Resumen de Cmos design for intersymbol interference cancellation in high-speed serial communications
In a digital communications system, intersymbol interference is an overlapping in time between consecutive transmitted bits. It is a major drawback in high-speed serial links, which must be cancelled to achieve an error-free communication between a transmitter and a receiver.
CMOS Design for Intersymbol Interference Cancellation in High-Speed Serial Communications explores different techniques to cancel intersymbol interference in multigigabit applications, focusing on duobinary baseband modulation. Using this technique, an excellent trade-off between speed, signal integrity and power consumption is achieved. Two different prototypes working at 3.125 Gbps and 10 Gbps are demonstrated using, respectively, a bulk CMOS and a silicon on insulator CMOS process.
