Cafm nanoscale electrical characterization of gate stacks for advanced mos devices
- Autores: Mario Lanza Martinez
- Directores de la Tesis: Marc Porti i Pujal (dir. tes.)
- Lectura: En la Universitat Autònoma de Barcelona ( España ) en 2010
- Idioma: inglés
- Tribunal Calificador de la Tesis: Germán González Díaz (presid.), Jorge Francisco Suñe Tarruella (secret.), P.K. Hurley (voc.)
- Materias:
- Enlaces
- Tesis en acceso abierto en: TESEO
- Resumen
In the current digital era, from our houses to our offices, in the subway and at the restaurant, we are surrounded by thousands of microelectronics based products that make our life easier, as for example, our inseparable mobile phone. The huge technological development that humanity has experienced would have not been possible without the constant electronics evolution. One of the main causes of this revolution has been the progressive dimensions reduction of a key device placed in almost every electronic set: the MOSFET transistor. The importance of the MOSFET transistor in microelectronics relies on the large number of them present at any simple chip (actually, it is considered the most times reproduced human invention). In digital circuits, it mostly plays the role of a tiny switch which defines the two logic states of the binary code (that is, the popular 0 and 1 responsible for storing the information). Taking into account that (at least) one MOSFET transistor is needed to store a bit of information, and that nowadays the hard disk of our computers can store around 250 GB of data, it is possible to understand the importance of its reduced size. Furthermore, smaller MOSFET transistors imply faster transitions from one to the other logical state or, in other words, an increase of the operation speed. For these reasons, many companies as IBM or Samsung (among others) are spending a lot of time and money to study the miniaturization of the MOSFET transistor, which recently started to achieve nanometric sizes.
But the scaling down of the MOSFET transistor is not an easy process. It has been observed that the dimension reduction of the electronic devices leads to new reliability and variability problems. For example, the progressive reduction of the device dimensions without the corresponding scaling down of the supply voltages leads to larger leakage currents (which implies higher power consumption) and, consequently, to an impoverishment of the reliability of the transistor. To solve these problems, it seems inevitable the introduction of some variations in the present technology if the major semiconductor companies requests want to be achieved. From the different solutions proposed, in the case of the gate stack, the replacement of the SiO2 by other materials could be an alternative.
The substitution of the SiO2 by a dielectric with a higher permittivity would allow using thicker stacks and, therefore, that would reduce the leakage currents. Even if this sounds very reasonable, it supposes a big challenge for the industry, since a material with only one advantage (high-k dielectric) is going to replace another (SiO2) that only shows one drawback: a small dielectric constant. The main problems related to the use of high-k dielectrics based stacks are: i) high density of intrinsic defects, ii) bad interaction with the gate electrode, iii) unavoidable formation of a SiO2 layer at the interface with the Silicon substrate, iv) poor carrier's mobility at the conductive channel due to scattering phonons, and iv) changes in the morphology depending on the manufacturing process (such as crystallization) which can alter their electrical properties, among others. For these reasons although, to date, the semiconductors industry is still using SiO2 (or SiON), huge efforts are devoted to study high-k materials. Currently, some companies, such as Intel, are already using high-k dielectrics in CMOS applications.
Since many of the problems associated to the high-k dielectrics (like, for example, their crystallization) and the failure mechanisms that affect to the gate oxide reliability are phenomena that have been found to have a nanometric origin, it seems obvious that, if an accurate knowledge wants to be obtained, they have to be studied at the nanoscale. The different techniques that recently have been used to perform such nanoscale analyses are the Scanning Probe based techniques. Among them, especially when studying the electrical properties and reliability of gate dielectrics, the Conductive Atomic Force Microscope (CAFM) has been the most used until now. This technique is capable to obtain simultaneously and independently topographical and electrical information at the nanoscale, achieving lateral resolutions of the order of 10nm.
In this context, this thesis will show the approaches adopted at the Reliability of Electron Devices and Circuits group (REDEC) of the UAB to evaluate with CAFM the nanoscale properties and failure mechanisms related to MOS gate stacks. Chapter 1 will be devoted to introduce the MOSFET transistor and the actual problematic related to its scaling down. The second chapter will provide an accurate explanation of the fundamental tool used in this thesis to study thin oxides at the nanoscale: the CAFM. Afterwards, the results obtained on SiO2 and high-k based samples (provided by Infineon Technologies, Numonyx and Qimonda) will be presented. In Chapter 3, CAFM has been used to investigate at the nanoscale, the electrical properties (before BD) of SiO2 tunnel oxides (for non-volatile memory applications) that have been previously subjected to an electrical stress at the device level. In particular, the generation of defects and its impact on leakage current and charge trapping have been analyzed in detail. Chapter 4 will be dedicated to high-k dielectrics. In particular, the impact of some manufacturing processes on the electrical properties of Hafnium and Aluminum based gate stacks will be evaluated. Specifically, the effect of an annealing process on the morphological and electrical properties of the stack will be analyzed. As Chapter 4 will show, although a CAFM (working in air) provides a large resolution (~10nm), sometimes it cannot be enough. In these cases, a solution is to measure in controlled environments. Chapter 5 will be dedicated to analyze the main advantages and drawbacks when using a CAFM in ultra high vacuum and dry Nitrogen environments.
