Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

• Raghavendra Rao N.S. ^[1] ; Chitra A. ^[1]
  1. [1] Vellore Institute of Technology, India
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 42, Nº 2, 2023, págs. 585-604
• Idioma: inglés
• Enlaces
  • Texto completo
• Resumen

  • Purpose The purpose of this study is to extend a sensitivity-based reliability technique for the processors deployed in industrial drive (ID).

    Design/methodology/approach The processor provides flexible operation, re-configurability, and adaptable compatibility in industrial motor drive system. A sensitivity-based model allows a robust tool for validating the system design. Sensitivity is the probability of a partial failure rate for a distributed variable; sensitivity and failure rates are also complementary. Conversely, traditional power electronic components reliability estimating standards have overlooked it, and it is essential to update them to account for the sensitivity parameter. A new sensitivity-based reliability prediction methodology for a typical 32-bit microprocessor operating at 30ºC deployed in ID is presented to fill this gap. The proposed techniques are compared with the estimated processor reliability values obtained from various reliability standards using the validated advanced logistics development tool. The main contribution of this work is to provide a sensitivity extended reliability method over the conventional method directing toward improving reliability, availability, and maintainability in the design of ID.

    Findings The analysis shows that the sensitivity of the processor’s circuit increases due to increases in complexity of the system by reducing the overall mean time between failure upon comparing among conventional reliability standards.

    Originality/value The significance of this paper lies in the overall, sensitivity-based reliability technique for processors in comparison to the traditional reliability complexity in IDs.