Resumen de Systolic architecture design for decoding convolutional codes using Viterbi algorithm

Sadiq M Sait, Ali F. Damati, Mushfiqur Rahman

• The paper proposes a systolic algorithm for Viterbi decoding, and provides an architecture which is well-suited for VLSI implementation. The algorithm has been modeled in RTL (register transfer level), and simulated for functional correctness. The adventages of the algortihm are also mentioned.